LM12454, LM12458, LM12H458
SNAS079A – MAY 2004 – REVISED FEBRUARY 2006
6.0 Design Considerations
6.1 REFERENCE VOLTAGE
The difference in the voltages applied to the VREF+ and VREF− defines the analog input voltage span (the
difference between the voltages applied between two multiplexer inputs or the voltage applied to one of the
multiplexer inputs and analog ground), over which 4095 positive and 4096 negative codes exist. The voltage
sources driving VREF+ or VREF− must have very low output impedance and noise.
The ADC can be used in either ratiometric or absolute reference applications. In ratiometric systems, the analog
input voltage is proportional to the voltage used for the ADC's reference voltage. When this voltage is the system
power supply, the VREF+ pin is connected to VA+ and VREF− is connected to GND. This technique relaxes the
system reference stability requirements because the analog input voltage and the ADC reference voltage move
together. This maintains the same output code for given input conditions.
For absolute accuracy, where the analog input voltage varies between very specific voltage limits, a time and
temperature stable voltage source can be connected to the reference inputs. Typically, the reference voltage's
magnitude will require an initial adjustment to null reference voltage induced full-scale errors.
When using the LM12(H)454/8's internal 2.5V bandgap reference, a parallel combination of a 100
and a 0.1
μF capacitor connected to the VREFOUT pin is recommended for low noise operation. When left
unconnected, the reference remains stable without a bypass capacitor. However, ensure that stray capacitance
at the VREFOUT pin remains below 50 pF.
6.2 INPUT RANGE
The LM12(H)454/8's fully differential ADC and reference voltage inputs generate a two's-complement output that
is found by using the equation below.
Round up to the next integer value between
−4096 to 4095 for 12-bit resolution and between −256 to 255 for 8-
bit resolution if the result of the above equation is not a whole number. As an example, VREF+ = 2.5V, VREF− = 1V,
VIN+ = 1.5V and VIN− = GND. The 12-bit + sign output code is positive full-scale, or 0,1111,1111,1111. If VREF+ =
5V, VREF− = 1V, VIN+ = 3V, and VIN− = GND, the 12-bit + sign output code is 0,1100,0000,0000.
6.3 INPUT CURRENT
A charging current flows into or out of (depending on the input voltage polarity) the analog input pins, IN0–IN7 at
the start of the analog input acquisition time (tACQ). This current's peak value will depend on the actual input
voltage applied. This charging current causes voltage spikes at the inputs. This voltage spikes will not corrupt the
6.4 INPUT SOURCE RESISTANCE
For low impedance voltage sources (<100
Ω for 5 MHz operation and <60Ω for 8 MHz operation), the input
charging current will decay, before the end of the S/H's acquisition time, to a value that will not introduce any
conversion errors. For higher source impedances, the S/H's acquisition time can be increased. As an example,
operating with a 5 MHz clock frequency and maximum acquisition time, the LM12(H)454/8's analog inputs can
handle source impedance as high as 6.67 k
Ω. When operating at 8 MHz and maximum acquisition time, the
LM12H454/8's analog inputs can handle source impedance as high as 4.17 k
Ω. Refer to Section 2.1, Instruction
RAM “00”, Bits 12–15 for further information.
6.5 INPUT BYPASS CAPACITANCE
External capacitors (0.01
μF to 0.1 μF) can be connected between the analog input pins, IN0–IN7, and analog
ground to filter any noise caused by inductive pickup associated with long input leads. It will not degrade the
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