LM12454_14 datasheet(40/45 Pages) TI1 | LM12454/LM12458/LM12H458 12-Bit + Sign Data Acquisition System with Self-Calibration

Part No.	LM12454

Description	LM12454/LM12458/LM12H458 12-Bit Sign Data Acquisition System with Self-Calibration

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LM12454, LM12458, LM12H458

SNAS079A – MAY 2004 – REVISED FEBRUARY 2006

www.ti.com

Improper termination of digital lines. Improper termination can result in energy reflections that build up to

cause overshoot that goes above the supply potential and undershoot that goes below ground. It is never good

to drive a device beyond the supply rails, unless the device is specifically designed to handle this situation, but

the LM12(H)458 is more sensitive to this condition that most devices. Again, if any pin experiences a potential

more than 100 mV below ground or above the supply voltage, even on a fast transient basis, the result could be

erratic operation, missing codes, or a complete malfunction, depending upon how far the input is driven beyond

the supply rails. The clock input is the most sensitive digital one. Generally, a 50

Ω series resistor, located very

close to the signal source, will keep digital lines "clean".

Excessive output capacitance on the digital lines. The current required to charge the capacitance on the

digital outputs can cause noise on the supply bus within the LM12(H)458, causing internal supply "bounce" even

when the external supply pin is pretty stable. The current required to discharge the output capacitance can cause

die ground "bounce". Either of these can cause noise to be induced at the analog inputs, resulting in conversion

errors.

Output capacitance should be limited as much as possible. A series 100

Ω resistor in each digital output line,

located very close to the output pin, will limit the charge and discharge current, minimizing the extent of the

conversion errors.

Improper CS decoding. If address decoder is used, care must be exercised to ensure that no "runt" (very

narrow) pulse is produced on theCS line when trying to address another device or memory. Even sub-

nanosecond spikes on the CS line can cause the chip to be reprogrammed in accordance with what happens to

be on the data lines at the time. The result is unexpected operation. The worst case result is that the device is

put into the "Test" mode and the on-board EEPROM that corrects linearity is corrupted. If this happens, the only

recourse is to replace the device.

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