LM12454_14 datasheet(8/45 Pages) TI1 | LM12454/LM12458/LM12H458 12-Bit + Sign Data Acquisition System with Self-Calibration

Part No.	LM12454

Description	LM12454/LM12458/LM12H458 12-Bit Sign Data Acquisition System with Self-Calibration

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Manufacturer	TI1 [Texas Instruments]

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LM12454, LM12458, LM12H458

SNAS079A – MAY 2004 – REVISED FEBRUARY 2006

www.ti.com

Converter AC Characteristics

(1) (2) (3) (4)

The following specifications apply to the LM12454, LM12458, and LM12H458 for VA+ = VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12-

bit + sign conversion mode, fCLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS = 25Ω, source impedance for

VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless

otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.

Symbol

Parameter

Conditions

Typical (5)

Limits (6)

Units

%

Clock Duty Cycle

50

40

% (min)

60

% (max)

13-Bit Resolution, Sequencer State

44 (tCLK)

44 (tCLK) + 50 ns

(max)

S5 (Figure 14)

tC

Conversion Time

9-Bit Resolution, Sequencer State S5

21 (tCLK)

21 (tCLK) + 50 ns

(max)

(Figure 14)

Sequencer State S7 (Figure 14) Built-

9 (tCLK)

9 (tCLK) + 50 ns

(max)

in minimum for 13-Bits

tA

Acquisition Time

Built-in minimum for 9-Bits and

2 (tCLK)

2 (tCLK) + 50 ns

(max)

“Watchdog” mode

tZ

Auto-Zero Time

Sequencer State S2 (Figure 14)

76 (tCLK)

76 (tCLK) + 50 ns

(max)

tCAL

4944 (tCLK) + 50

Full Calibration Time

Sequencer State S2 (Figure 14)

4944 (tCLK)

(max)

ns

89

88

kHz (min)

Throughput Rate (7)

LM12H458

142

140

kHz (min)

“Watchdog” Mode Comparison Time

Sequencer States S6, S4, and S5

tWD

11 (tCLK)

11 (tCLK) + 50 ns

(max)

(Figure 14)

VIN = ±5V

fIN = 1 kHz

77.5

dB

DSNR

Differential Signal-to-Noise Ratio

fIN = 20 kHz

75.2

dB

fIN = 40 kHz

74.7

dB

VIN = 5 Vp-p

fIN = 1 kHz

69.8

dB

SESNR

Single-Ended Signal-to-Noise Ratio

fIN = 20 kHz

69.2

dB

fIN = 40 kHz

66.6

dB

VIN = ±5V

fIN = 1 kHz

76.9

dB

Differential Signal-to-Noise +

DSINAD

Distortion Ratio

fIN = 20 kHz

73.9

dB

fIN = 40 kHz

70.7

dB

VIN = 5 Vp-p

fIN = 1 kHz

69.4

dB

Single-Ended Signal-to-Noise +

SESINAD

Distortion Ratio

fIN = 20 kHz

68.3

dB

fIN = 40 kHz

65.7

dB

(1)

Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above

VA+ or 5V below GND will not damage the LM12454 or the LM12(H)458. However, errors in the A/D conversion can occur if these

diodes are forward biased by more than 100 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.6 VDC to ensure

accurate conversions.

(2)

VA+ and VD+ must be connected together to the same power supply voltage and bypassed with separate capacitors at each V

+ pin to

assure conversion/comparison accuracy.

(3)

Accuracy is guaranteed when operating at fCLK = 5 MHz for the LM12454/8 and fCLK = 8 MHz for the LM12H458.

(4)

With the test condition for VREF (VREF+ − VREF−) given as +5V, the 12-bit LSB is 1.22 mV and the 8-bit/“Watchdog” LSB is 19.53 mV.

(5)

Typical figures are at TA = 25°C and represent most likely parametric norm.

(6)

Limits are to AOQL (Average Output Quality Level).

(7)

The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock

cycles) and 5 (44 clock cycles) are used (see Figure 14). One additional clock cycle is used to read the conversion result stored in the

FIFO, for a total of 56 clock cycles per conversion. The Throughput Rate is fCLK (MHz)/N, where N is the number of clock

cycles/conversion.

8

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