Electronic Components Datasheet Search |
|
A3968SLBTR Datasheet(PDF) 6 Page - Allegro MicroSystems |
|
A3968SLBTR Datasheet(HTML) 6 Page - Allegro MicroSystems |
6 / 8 page Dual Full-Bridge PWM Motor Driver with Brake A3968 6 Allegro MicroSystems, LLC 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Internal PWM Current Control. The A3968 dual full-bridges bidirectionally control two DC motors. An internal fixed-frequency PWM control circuit controls the the load current in each motor. The current-control circuitry works as follows: when the outputs of the full-bridge are turned on, current increases in the motor winding. The load current is sensed by the current-control comparator via an external sense resistor. RS. Load current continues to increase until it reaches the predetermined value, set by the selection of external current-sensing resistors and reference input voltage (VREF) according to the equation: ITRIP = IOUT + ISO = VREF/(4 RS) where ISO is the sense-current error (typically 18 mA) due to the base-drive current of the sink driver transistor. At the trip point, the comparator resets the source-en- able latch, turning off the source driver of that full-bridge. The source turn-off of one full-bridge is independent of the other full-bridge. Load inductance causes the current to recirculate through the sink driver and ground-clamp diode. The current decreases until the internal clock oscillator sets the source-enable latches of both Full-bridges, turning on the source drivers of both bridges. Load current increases again, and the cycle is repeated. The frequency of the internal clock oscillator is set by the external timing components RTCT. The frequency can be approximately calculated as: fosc = 1/(RT CT + tblank) where tblank is defined below. The range of recommended values for RT and CT are 20 to 100 k and 470 to 1000 pF respectively. Nominal values of 56 k and 680 pF result in a clock frequency of 25.4 kHz. Current-Sense Comparator Blanking. When the source driver is turned on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and switch- ing transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the current-control comparator output is blanked for a short period of time when the source driver is turned on. The blanking time is set by the timing compo- nent CT according to the equation: tblank = 1900 CT (μs). A nominal CT value of 680 pF will give a blanking time of 1.3 μs. The current-control comparator is also blanked when the load current changes polarity (direction or phase change). This internally generated blank time is approxi- mately 1.8 μs. FUNCTIONAL DESCRIPTION + – 0 Dwg. WM-003-2 VPHASE I OUT t d ITRIP t blank INTERNAL OSCILLATOR BRIDGE ON SOURCE OFF BRIDGE ON R C T T ALL OFF Enlargement A See Enlargement A Dwg. EP-006-16 R S BB V BRIDGE ON SOURCE OFF ALL OFF |
Similar Part No. - A3968SLBTR |
|
Similar Description - A3968SLBTR |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |