1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

SVDD

SCL

SDA

REF

SADJ

LADJ

RON

VO

COMP

NC

EN/UVLO

VIN

VCC

BOOT

GATE

SW

LNG

LNCS

CS

GND

NC – No internal connection

Exposed

Thermal

Pad

TPS92660

SLUSBC2 – APRIL 2013

www.ti.com

DEVICE INFORMATION

TSSOP PACKAGE

20-PINS

(TOP VIEW)

NAME

NO.

I/O

DESCRIPTION

SVDD

1

P

SCL

2

I

SDA

3

I/O

REF

4

O

3.0V output reference.

SADJ

5

I

Switching regulator dimming input.

LADJ

6

I

Linear regulator dimming input.

RON

7

I

Connect to resistor and capacitor which sets the switching frequency of the switching regulator.

VO

8

I

Output voltage sense for control and protection.

COMP

9

O

Switching regulator error amplifier (EA) compensation connection.

NC

10

-

No internal connection.

GND

11

G

System ground connection.

CS

12

I

Switching regulator LED Current sense input.

LNCS

13

I

Linear regulator current sense input.

LNG

14

O

Linear FET gate driver output.

SW

15

I

Connect to the switch node of the switching regulator.

GATE

16

O

Switching controller high-side N-channel FET driver output.

BOOT

17

I

MOSFET drive bootstrap pin.

VCC

18

O

Output of internal regulator. Bypass it with 1µFminimum ceramic capacitor to GND.

VIN

19

P

Input voltage supply for device. Maximum of 80V operating voltage.

EN/UVLO

20

I

This pin is a multi function input. Enable of device, Under-voltage lock-out (UVLO).

DAP

-

-

Exposed thermal pad. Connected to the system ground. Place vias on DAP.

(1)

I=Input, O=Output, P=Power, G=Ground

6

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