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SP791CN-L Datasheet(PDF) 10 Page - Sipex Corporation |
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SP791CN-L Datasheet(HTML) 10 Page - Sipex Corporation |
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10 / 19 page  SP791DS/08 SP791 Low Power Microprocessor Supervisory with Battery Switch-Over © Copyright 2000 Sipex Corporation 10 WATCHDOG FUNCTION The watchdog monitors µP activity via the Watchdog Input (WDI). If the µP becomes in- active over a period of time, WDO and WDPO are asserted. To use the watchdog functon, connect WDI to a bus line or µP I/O line. If WDI remains high or low for longer than the watchdog timeout period (1.6sec nominal), WDPO and WDO are asserted, indicating a software fault or idle condition. WATCHDOG INPUT A change of logic state (minimum 100ns dura- tion) at WDI during the watchdog period will reset the watchdog timer. The watchdog default timeout is 1.6sec. To select an alternative timeout period, connect an external capacitor from SWT to GND. To disable the watchdog function, leave WDI floating. An internal impedance network (100k Ω equivalent at WDI) biases WDI to approximately 1.6V. Internal comparators detect this level and disable the watchdog timer. When Vcc is below the reset threshold, the watchdog function is dis- abled and WDI is disconnected from its internal network, thus becoming high impedance. WATCHDOG OUTPUT WDO remains high if there is activity (transi- tion or pulse) at WDI during the watchdog- timeout period. The watchdog function is dis- abled and WDO is a logic high when VCC is less than the reset threshold, or when WDI is an open circuit. In watchdog mode, if no transi- tion occurs at WDI during the watchdog-timeout period, WDO goes low 70ns after the falling edge of WDPO and remains low until the next transition at WDI as shown on Figure 5. A flip- flop can force the system into a hardware shut- down if there are two successive watchdog faults, shown on Figure 6. WDO has a 2 x TTL output characteristic. WATCHDOG-PULSE OUTPUT As described in the preceding section, WDPO can be used as the clock input to an external D flip-flop. Upon the absence of a watchdog edge or pulse at WDI at the end of a watchdog-timeout period, WDPO will pulse low for 1ms. The fall- ing edge of WDPO precedes WDO by 70ns. Since WDO is high when WDPO goes low, the Q output of the flip-flop remains high as WDO goes low (Figure 6). If the watchdog timer is not reset by a transition at WDI, WDO remains low and WDPO clocks a logic low to the Q out- put, causing the SP791 to latch in reset. If the watchdog timer is reset by a transition at WDI, WDO goes high and the flip-flop's Q output re- mains high. Thus, a system shutdown is only caused by two successive watchdog faults. The internal pull-up resistors associated with WDO and WDPO connect to VOUT. Therefore, do not connect these outputs directly to CMOS logic that is powered from VCC since, in the ab- sence of VCC (i.e., battery mode), excessive current will flow from WDO or WDPO through the protection diode(s) of the CMOS-logic in- puts to ground. SELECTING AN ALTERNATIVE WATCHDOG TIMEOUT PERIOD SWT input controls the watchdog-timeout pe- riod. Connecting SWT to VOUT selects the in- ternal 1.6sec watchdog-timeout period. Select an alternative timeout period by connecting a capacitor between SWT and GND. Do not leave SWT floating, and do not connect it to ground. The following formula determines the watch- dog-timeout period: Watchdog Timeout Period = 2.1 x (capacitor value in nF) ms This formula is valid for capacitance values between 4.7 nF and 100nF (see the Watchdog Timeout vs. Timing Capacitor graph in the Typi- cal Operating Characteristics). CHIP-ENABLE SIGNAL GATING The SP791 provides internal gating of chip-en- able (CE) signals to prevent erroneous data from corrupting the CMOS RAM in the event of a power failure. During normal operation, the CE gate is enabled and passes all CE transitions. When reset is asserted, this path becomes dis- abled, preventing erroneous data from corrupt- ing the CMOS RAM. The SP791 uses a series transmission gate from CE IN to CE OUT. |
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