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74AHC30 Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AHC30 Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 14 page 74AHC_AHCT30_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 26 June 2009 3 of 14 NXP Semiconductors 74AHC30; 74AHCT30 8-input NAND gate 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 74AHC30 74AHCT30 AVCC B n.c. CH DG E n.c. F n.c. GND Y 001aai162 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aak237 74AHC30 74AHCT30 Transparent top view F GND(1) n.c. E n.c. DG CH B n.c. 6 9 5 10 4 11 3 12 2 13 terminal 1 index area Table 2. Pin description Symbol Pin Description A 1 data input B 2 data input C 3 data input D 4 data input E 5 data input F 6 data input GND 7 ground (0 V) Y 8 data output n.c. 9 not connected n.c. 10 not connected G 11 data input H 12 data input n.c. 13 not connected VCC 14 supply voltage |
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