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HD155101BF Datasheet(PDF) 10 Page - Hitachi Semiconductor |
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HD155101BF Datasheet(HTML) 10 Page - Hitachi Semiconductor |
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10 / 50 page  HD155101BF 10 3 RFOUT Poutput Pinput 6 RFIN 4 Vcc VCCLNA 5 GNDLNA LNA bias circuit LNA Vref Figure 1 LNA Bias Circuit Transmitter Operation The transmitter chain converts differential IQ baseband signals to a suitable format for transmission by a power amplifier. The common mode DC voltage range of the modulator inputs is 0.8 to 1.2 V and they have 2.4 Vp-p Max differential swing. The modulator circuit uses double-balanced mixers for the I and Q paths. The LO signals are generated by dividing the IFLO signal by 2 and then passing them through a phase splitter / shifter. The IF signals generated are then summed and produce a single modulated IF signal which is amplified and fed into the offset PLL block. Carrier suppression due to the mixer circuit is better than 31 dBc. However, if the common mode DC voltage of the I and Q inputs is adjusted, carrier suppression can be improved better than 40 dBc easily. In addition, upper side-band suppression is better than 35 dBc. Within the offset PLL block there is a down converter, a phase comparator and a VCO driver. The down converter mixes the 1st LO signal and the TX VCO to create a reference LO signal for use in the offset PLL circuit. The phase comparator and the VCO driver generate an error current, which is proportional to the phase difference between the reference IF and the modulated IF signals. This current is used in a 2nd order loop filter to generate a voltage, which in turn modulates the TX VCO. In order to optimize the PLL loop gain, the error current value can be modified by changing the value of an external resistor - ICURAD. In order to accommodate a range of TX VCO, the offset PLL circuit has been designed to operate with a supply voltage of up to 5.25 V. Operating Modes The HD155101BF has the necessary control circuitry to implement the necessary states within the GSM system. Also provided is a power save mode which reduces the current consumption of the device by powering down unnecessary function blocks. Three pins are assigned for mode control, POONRX1, POONRX2 and POONTX. Table 1 shows the relationship between the pins and the required operating mode. Control of these pins are by the system controller. As per GSM requirements the TX and RX sections are not on at the same time. For the receiver there is a calibration mode for which the LNA bias circuit and 1st mixer are switched off. During this period the gain of the AGC can be adjusted. Also the DC offsets of the IQ demodulator are measured and subsequently canceled. In order to change between the RX and TX modes a state called “warm-up” is used to ensure that the LO signals are not unduly affected. This method of switching between TX and RX ensures that lock is achieved first time. |
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