8

HV5408B

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

44-Lead Quad Cerpac/PLCC Pin Assignment (DJ/PJ)

Pin

Function

Description

1

HV

High voltage outputs.

High voltage push-pull outputs, which, depending on controlling low voltage data,

can drive loads either to GND, or to V

2

HV

3

HV

4

HV

5

HV

6

HV

7

HV

8

HV

9

HV

10

HV

11

HV

12

HV

13

HV

14

HV

15

HV

16

HV

17

HV

18

DATA OUT

Serial data output.

Data output for cascading to the data input of the next device.

19

N/C

No connect.

20

21

22

CLK

Data shift register clock

Input are shifted into the shift register on the positive edge of the clock.

23

GND

Logic and high voltage ground.

24

VPP

High voltage power rail.

25

VDD

Low voltage logic power rail.

26

LE

Latch enable input.

When LE is HIGH, shift register data is transferred into a data latch. When LE is

LOW, data is latched, and new data can be clocked into the shift register.

27

DATA IN

Serial data input.

Data needs to be present before each rising edge of the clock.