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TP2104 Datasheet(PDF) 1 Page - Supertex, Inc |
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TP2104 Datasheet(HTML) 1 Page - Supertex, Inc |
1 / 6 page ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com TP2104 General Description This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally- induced secondary breakdown. Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. P-Channel Enhancement Mode Vertical DMOS FETs Absolute Maximum Ratings Pin Configuration Product Marking TO-236AB (SOT-23) (K1) P1LW W = Code for week sealed = “Green” Packaging DRAIN SOURCE GATE Ordering Information Device Package Options BV DSS/BVDGS (V) R DS(ON) (max) (Ω) V GS(th) (max) (V) TO-236AB (SOT-23) TO-92 TP2104 TP2104K1-G TP2104N3-G -40 6.0 -2.0 -G indicates package is RoHS compliant (‘Green’) Parameter Value Drain-to-source voltage BV DSS Drain-to-gate voltage BV DGS Gate-to-source voltage ±20V Operating and storage temperature -55°C to +150°C Soldering temperature* +300°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. GATE SOURCE DRAIN TO-92 (N3) TO-236AB (SOT-23) (K1) YY = Year Sealed WW = Week Sealed = “Green” Packaging SiTP 2 1 0 4 Y Y W W TO-92 (N3) Features High input impedance and high gain Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability Integral source-drain diode Free from secondary breakdown Applications Logic level interfaces - ideal for TTL and CMOS Solid state relays Analog switches Power management Telecom switches ► ► ► ► ► ► ► ► ► ► ► ► Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or |
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