11

HV461

Pin

Name

Description

1

DCREF3

See DCREF1 and DCREF2 (pins 47 & 48).

2

VREF1

Outputs a 1.25V nominal reference voltage. Bypass with a 100nF capacitor to ground.

3

VREF2

Outputs a 2.50V nominal reference voltage. Bypass with a 100nF capacitor to ground.

4

AVDD

Supply for the analog section. 3.0 to 3.6V Must be from the same source as DVDD. Bypass with

a 100nF capacitor to ground as close as possible to the IC.

5

TSYNC

An RC network connected to this pin determines the SYNC pulse lead time (see SYNC pin 14).

t

6

XTAL

A crystal from this pin to ground provides the frequency reference for the internal sine wave

synthesizer. A 19.6608MHz baud rate crystal provides the 8 most common ring frequencies. The

crystal is operated in the series mode. A loading capacitor is not necessary. See also FREQ0–2

(pins 21–23) and FRING (pin 7).

7

FRING

Ring frequency is normally selected from the 8 built-in frequencies using control inputs FREQ0–

2. Other arbitrary frequencies in the range of 12 to 63Hz may be obtained by applying an external

signal to FRING. This external signal sets the ring frequency at a 1:1 ratio. The ring signal

remains a sine wave, with amplitude and offset still controlled via AMPx and OFFx. The ring

signal, while frequency locked to the FRING signal, is not phase–synchronized to it. This allows

the ring signal to immediately start at 0º when enabled via ENABLE or AMP ≠ 00. When unused,

this input must be connected to VGD.

8

PLLFLT

Phase locked loop filter. An RC network connected to this pin stabilizes the PLL that locks on to

the optional external ring frequency signal. (See FRING, pin 7) The RC network determines the

lock time of the PLL. Due to the low frequencies involved, it may take a couple seconds to lock

to the external signal. See the typical application schematic for typical values. When unused, this

pin should be left unconnected.

9

ROSC

A resistor from this pin to VDD sets the PWM frequency. f

150kHz)

10

RESET

A capacitor from this pin to ground provides a power–on reset interval. It has an internal 10µA

pull–up to charge the external reset capacitor. Alternatively, an external logic–level or open–

drain signal may be applied to implement the reset function. During the reset interval when

V

time for the host controller to assume control. Use a low leakage tantalum or ceramic capacitor.

t

11

PWMSYNC

This pin functions as both an input and an output. It is open–drain with an internal 100µA pull-

up. As an output, it provides a short, low-going pulse at the internal PWM frequency. As an

input, it synchronizes internal PWM frequency to the externally applied signal, provided the

external signal is at a higher frequency. The low-going applied sync pulse should be between

25ns and less than the PWM period in duration. The external source should be open drain. If

the PWMSYNC pins of multiple HV461s are tied together, their PWM frequencies will be phase-

locked to the HV461 with the highest free-running frequency. A maximum of 10 HV461s may be

tied together. If unused, this pin should be left unconnected.

12

CFAULT

A capacitor from this pin to ground sets the integration time of the FAULT detection circuitry.

A larger capacitor provides less suseptability to transient problems, while a smaller capacitor

provides quicker response. Values in the range of 1µF to 100µF are appropriate. If the FAULT

output is not used, this pin should be grounded. See also FAULT (pin 15).