BU4S01G2,BU4S11G2,BU4SU69G2,BU4S71G2,BU4S81G2, BU4S584G2

Technical Note

2/16

www.rohm.com

2009.06 - Rev.A

© 2009 ROHM Co., Ltd. All rights reserved.

When used at Ta=25[°C] or above, values of above are reduced per 1[°C].

Power dissipation is the value for mounting 70[mm] x 70[mm] x 1.6[mm]

FR4 glass epoxy circuit board (copper foil area is 3% or less).

●

Absolute Maximum Ratings

Parameter

Symbol

Limit

Unit

BU4S01G2 BU4S11G2 BU4SU69G2 BU4S71G2 BU4S81G2 BU4S584G2

Power supply voltage

VDD

-0.3 to 18

V

Supply current

Iin

±10

mA

Operating temperature

Topr

-40 to 85

℃

Storage temperature

Tstg

-55 to 150

℃

Input voltage

VIN

-0.3 to VDD+0.3

V

Maximum junction temperature

Tjmax

150

℃

●

Recommended Operating Conditions

Parameter

Symbol

Limit

Unit

BU4S01G2 BU4S11G2 BU4SU69G2 BU4S71G2 BU4S81G2 BU4S584G2

Operating power supply

VDD

3 to 16

V

Input voltage

VIN

0 to VDD

V

●

Thermal Derating Curve

●

Input / output Equivalent Circuits

●

Switching Characteristics

(*1)

UNIT

5.3

mW/℃

＜

＜

Output＞

VDD

GND

VDD

GND

VDD

VDD

GND

GND

Description of symbols

(1) tPHL: Time up to 50% of rise time of input waveform

~ 50% of fall time of output waveform

(2) tPLH: Time up to 50% of fall time of input waveform

~ 50% of rise time of output waveform

(3) tTHL: Time up to 90% ~ 10% of fall time of output waveform

(4) tTLH: Time up to 10% ~ 90% of rise time of output waveform

Description of symbols

(1) tPLH: Time up to 50% of rise time of input waveform

~50% of rise time of output waveform

(2) tPHL: Time up to 50% of fall time of input waveform

~ 50% of fall time of output waveform

(3) tTLH: Time up to 10% ~ 90% of rise time of output waveform

(4) tTHL: Time up to 90% ~ 10% of fall time of output waveform

0

200

400

600

800

1000

1200

1400

0

25

50

75

100

125

150

175

Ambient 　temperature　 Ta〔℃〕

670[mV] BU4S Series (＊1)

85℃

BU4S01G2

BU4S11G2

BU4SU69G2

BU4S71G2

BU4S81G2

BU4S584G2

90%

50%

10%

10%

50%

90%

20[ns]

20[ns]

Input

Output

①

tPHL

②

tPLH

③

tTHL

④

tTLH

90%

50%

10%

90%

50%

10%

20[ns]

20[ns]

④

tTHL

①

tpLH

Input

Output

③

tTLH

②

tpHL