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HM62W16255HCLJP-10 Datasheet(PDF) 9 Page - Hitachi Semiconductor

Part # HM62W16255HCLJP-10
Description  4M High Speed SRAM (256-kword x 16-bit)
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Manufacturer  HITACHI [Hitachi Semiconductor]
Direct Link  http://www.renesas.com/eng
Logo HITACHI - Hitachi Semiconductor

HM62W16255HCLJP-10 Datasheet(HTML) 9 Page - Hitachi Semiconductor

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HM62W16255HC Series
9
Write Cycle
HM62W16255HC
-10
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t
WC
10
ns
Address valid to end of write
t
AW
7—
ns
Chip select to end of write
t
CW
7
ns
8
Write pulse width
t
WP
7
ns
7
Byte select to end of write
t
LBW, t UBW
7
ns
9, 10
Address setup time
t
AS
0
ns
5
Write recovery time
t
WR
0
ns
6
Data to write time overlap
t
DW
5—
ns
Data hold from write time
t
DH
0—
ns
Write disable to output in low-Z
t
OW
3
ns
1
Output disable to output in high-Z
t
OHZ
5
ns
1
Write enable to output in high-Z
t
WHZ
5
ns
1
Notes: 1. Transition is measured
±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. If the
CS or LB or UB low transition occurs simultaneously with the WE low transition or after the
WE transition, output remains a high impedance state.
3.
WE and/or CS must be high during address transition time.
4. If
CS, OE, LB and UB are low during this period, I/O pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
5. t
AS is measured from the latest address transition to the latest of CS, WE, LB or UB going low.
6. t
WR is measured from the earliest of CS, WE, LB or UB going high to the first address transition.
7. A write occurs during the overlap of low
CS, low WE and low LB or low UB.
8. t
CW is measured from the later of CS going low to the end of write.
9. t
LBW is measured from the later of LB going low to the end of write.
10. t
UBW is measured from the later of UB going low to the end of write.


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