HM62V8512C Series

8

Write Cycle

HM62V8512C

-5

-7

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write cycle time

t

WC

55

—

70

—

ns

Chip selection to end of write

t

CW

50

—

60

—

ns

4

Address setup time

t

AS

0—

0—

ns

5

Address valid to end of write

t

AW

50

—

60

—

ns

Write pulse width

t

WP

40

—

50

—

ns

3, 12

Write recovery time

t

WR

0—

0—

ns

6

WE to output in high-Z

t

WHZ

0

20

0

30

ns

1, 2, 7

Data to write time overlap

t

DW

25

—

30

—

ns

Data hold from write time

t

DH

0—

0—

ns

Output active from output in high-Z

t

OW

5—

5—

ns

2

Output disable to output in high-Z

t

OHZ

0

20

0

30

ns

1, 2, 7

Notes: 1. t

are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

3. A write occurs during the overlap (t

A write begins at the later

transition of

CS going low or WE going low. A write ends at the earlier transition of CS going high

or

WE going high. t

4. t

5. t

6. t

7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to

the outputs must not be applied.

8. If the

CS low transition occurs simultaneously with the WE low transition or after the WE transition,

the output remain in a high impedance state.

9. Dout is the same phase of the write data of this write cycle.

10. Dout is the read data of next address.

11. If

CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the

opposite phase to the outputs must not be applied to them.

12. In the write cycle with

OE low fixed, t

data bus contention. t