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HN58X2464FPI Datasheet(PDF) 8 Page - Hitachi Semiconductor |
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HN58X2464FPI Datasheet(HTML) 8 Page - Hitachi Semiconductor |
8 / 22 page HN58X2408I/HN58X2416I/HN58X2432I/HN58X2464I 8 Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to V CC or VSS. When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. As for 8k to 16k EEPROM, whole or some device address pins don't need to be fixed since device address code provided from the SDA pin is used as memory address signal. Pin Connections for A0 to A2 Pin connection Memory size Max connect number A2 A1 A0 Notes 8k bit 2 V CC/VSS* 1 ×*2 × Use A0, A1 for memory address a8 and a9 16k bit 1 ××× Use A0, A1, A2 for memory address a8, a9 and a10 32k bit 8 V CC/VSS V CC/VSS V CC/VSS 64k bit 8 V CC/VSS V CC/VSS V CC/VSS Notes: 1. “V CC/VSS” means that device address pin should be connected to VCC or VSS. 2. × = Don’t care (Open is also approval.) Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. WP should be fixed high or low during operations since WP does not provide a latch function. Write Protect Area Write protect area WP pin status 8k bit 16k bit 32k bit 64k bit V IH Upper 1/2 (4k bit) Upper 1/2 (8k bit) Upper 1/4 (8k bit) Upper 1/4 (16k bit) V IL Normal read/write operation |
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