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HT48CA0 Datasheet(PDF) 7 Page - Holtek Semiconductor Inc |
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HT48CA0 Datasheet(HTML) 7 Page - Holtek Semiconductor Inc |
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7 / 36 page  System Architecture Execution flow The HT48CA0 system clock can be derived from a crystal/ceramic resonator oscillator. It is in- ternally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipe- lined in such a way that a fetch takes one in- struction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an in- struction changes the program counter, two cy- cles are required to complete the instruction. Program counter – PC The 10-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify a maximum of 1024 addresses. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subrou- tine call, initial reset or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each in- struction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execu- tion, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise pro- ceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Mov- ing data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an addi- tional dummy cycle is required. Program memory – ROM The program memory is used to store the pro- gram instructions which are to be executed. It also contains data and table and is organized into 1024 ×14 bits, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: • Location 000H This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H. • Table location Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the con- tents of the lower-order byte to the specified Execution flow HT48CA0 7 23rd July ’98 |
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