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HT49C10 Datasheet(PDF) 10 Page - Holtek Semiconductor Inc |
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HT49C10 Datasheet(HTML) 10 Page - Holtek Semiconductor Inc |
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10 / 47 page  HT49C10 10 September 28, 1999 Instruction(s) Table Location *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table location tents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to TBLH (table higher-order byte register) (08H). Only the destination of the lower-order byte in the table is well-defined; the other bits of the table word are all transferred to the lower portion of TBLH, and the remaining two bits are both read as ²0². The TBLH is read only, and the ta- ble pointer (TBLP) is a read/write register (07H), indicating the table location. Before ac- cessing the table, the location should be placed in TBLP. All the table related instructions re- quire two cycles to complete the operation. These areas may function as a normal ROM dependingupontherequirements. Stack register - STACK The stack register is a special part of the mem- ory used to save the contents of the PC. The stack is organized into four levels and is neither part of the data nor part of the program, and is neither readable nor writeable. Its activated level is indexed by a stack pointer (SP) and is neither readable nor writeable. At a commence- ment of a subroutine call or an interrupt ac- knowledgment, the contents of the PC is pushed onto the stack. At the end of the subrou- tine or interrupt routine, signaled by a return instruction (RET or RETI), the contents of the PC is restored to its previous value from the stack. After chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the acknowledgment is still inhibited. Once the SP is decremented (by RET or RETI), the in- terrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure easily. Likewise, if the stack is full, and a ²CALL² is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent four return addresses are stored). Data memory - RAM The data memory (RAM) is designed with 81´8 bits, and is divided into two functional groups, namely special function registers and general purpose data memory, most of which are read- able/writeable, although some are read only. Of the two types of functional groups, the special function registers consist of an indirect addressing register 0 (00H), a memory pointer register 0 (MP0; 01H), an indirect addressing register 1 (02H), a memory pointer register 1 (MP1;03H), a bank pointer (BP;04H), an accumulator (ACC;05H), a program counter lower-order byte register (PCL;06H), a table pointer (TBLP;07H), a table higher-order byte register (TBLH;08H), a real time clock control register (RTCC;09H), a status register (STATUS;0AH), an interrupt control reg- ister 0 (INTC0;0BH), a timer/event counter (TMR;0DH), a timer/event counter control register (TMRC; 0EH), I/O registers (PA;12H, PB;14H), and interrupt control register 1 (INTC1;1EH). On the other hand, the general purpose data memory, addressed from 20H to 5FH, is used for data and control information under instruction commands. The areas in the RAM can directly handle arithmetic, logic, increment, decrement, and rotate operations. Except for some dedicated bits, each bit in the RAM can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indi- rectly accessible through the memory pointer Note: *9~*0: Table location bits @7~@0: Table pointer bits P9~P8: Current program counter bits |
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