Note:

1. WE must be high during all address transitions

4. During this period, I/O pins are in the output state, so the input signals of opposite phase to the outputs

should not be applied.

5. If the CS low transition occurs simultaneously or after with the WE low transition, the outputs remain in a

high impedance state

9. If CS is low during this period, then the I/O pins are in the output state and the data input signals of the

opposite phase to the outputs should not be applied

10. Transition is measured at

±500mV from the steady state

HT62L256

Rev. 0.00

7

August 15, 2002

Preliminary