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ARM920T Datasheet(PDF) 7 Page - ATMEL Corporation |
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ARM920T Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 350 page  ARM DDI 0151C Copyright © 2000, 2001 ARM Limited. All rights reserved. vii List of Tables ARM920T Technical Reference Manual Change history .............................................................................................................. ii Table 2-1 ARM9TDMI implementation options ......................................................................... 2-3 Table 2-2 CP15 register map .................................................................................................... 2-5 Table 2-3 Address types in ARM920T ...................................................................................... 2-6 Table 2-4 CP15 abbreviations ................................................................................................... 2-6 Table 2-5 Register 0, ID code ................................................................................................... 2-8 Table 2-6 Cache type register format ...................................................................................... 2-10 Table 2-7 Cache size encoding (M=0) .................................................................................... 2-11 Table 2-8 Cache associativity encoding (M=0) ....................................................................... 2-11 Table 2-9 Line length encoding ............................................................................................... 2-12 Table 2-10 Control register 1 bit functions ................................................................................ 2-12 Table 2-11 Clocking modes ....................................................................................................... 2-14 Table 2-12 Register 2, translation table base ............................................................................ 2-14 Table 2-13 Register 3, domain access control .......................................................................... 2-15 Table 2-14 Fault status register ................................................................................................. 2-16 Table 2-15 Function descriptions register 7 .............................................................................. 2-17 Table 2-16 Cache operations register 7 .................................................................................... 2-18 Table 2-17 TLB operations register 8 ........................................................................................ 2-19 Table 2-18 Accessing the cache lockdown register 9 ............................................................... 2-22 Table 2-19 Accessing the TLB lockdown register 10 ................................................................ 2-23 Table 3-1 CP15 register functions ............................................................................................. 3-4 Table 3-2 Level one descriptor bits ........................................................................................... 3-9 Table 3-3 Interpreting level one descriptor bits [1:0] ............................................................... 3-10 |
Similar Part No. - ARM920T_14 |
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Similar Description - ARM920T_14 |
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