7028L15PFG8 datasheet(1/17 Pages) IDT

Part #	7028L15PFG8

Description	True Dual-Ported memory cells which allow simultaneous reads of the same memory location

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Manufacturer	IDT [Integrated Device Technology]

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1

JANUARY 2009

DSC-4836/4

I/O

Control

Address

Decoder

64Kx16

MEMORY

ARRAY

7028

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0L

OEL

R/

WL

A15L

A0L

SEML

INT L

(2)

BUSYL

(1,2)

LBL

CE0L

OEL

UBL

I/O

Control

Address

Decoder

CE0R

OER

R/

WR

A15R

A0R

SEMR

INTR

(2)

BUSYR

(1,2)

LBR

R/WR

OER

UBR

M/

S

(2)

CE1L

CE0R

CE1R

4836 drw 01

I/O

CE1R

CE1L

8-15L

I/O

I/O0-7R

I/O8-15R

0-7L

R/WL

16

Functional Block Diagram

◆

M/

S = VIH for BUSY output flag on Master,

M/

S = VIL for BUSY input on Slave

◆

Interrupt Flag

◆

On-chip port arbitration logic

◆

Full on-chip hardware support of semaphore signaling

between ports

◆

Fully asynchronous operation from either port

◆

Separate upper-byte and lower-byte controls for multi-

plexed bus and bus matching compatibility

◆

TTL-compatible, single 5V (±10%) power supply

◆

Available in a 100-pin TQFP

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆

High-speed access

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

◆

Low-power operation

– IDT7028L

Active: 1W (typ.)

Standby: 1mW (typ.)

◆

Dual chip enables allow for depth expansion without

external logic

◆

IDT7028 easily expands data bus width to 32 bits or

more using the Master/Slave select when cascading more

than one device

HIGH-SPEED

64K x 16 DUAL-PORT

STATIC RAM

IDT7028L

NOTES:

1.

BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).

2.

BUSY and INT are non-tri-state totem-pole outputs (push-pull).

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