ICS580-01

Glitch-Free Clock Multiplexer

MDS 580-01 A

2

Revision 030300

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

Pin Assignment

DIV

Nominal Timeout

0

600 ns

1

75 ns

Timeout Selection

1

8

9

16

2

3

4

5

6

7

10

11

12

13

14

15

CLK1

VDDC

CLK2

NO_INA

DIV

OE4

GND

INA

INB

VDDI

OE3

GND

SELB

OE1

OE2

NO_INB

Pin Descriptions

Key: I = Input; O = output; P = power supply connection

Number

Name

Type

Description

1

SELB

I

Mux select. Selects INB when high. Internal pull-up.

2

DIV

I

Time out select. See table above. Internal pull-up.

3

VDDI

P

Supply for input clocks only. Can be higher than VDDC.

4

INA

I

Input Clock A.

5

INB

I

Input Clock B.

6

GND

P

Connect to ground.

7

OE4

I

Output Enable. Tri-states NO_INB when low. Internal pull-up.

8

OE3

I

Output Enable Tri-states NO_INA when low. Internal pull-up.

9

OE2

I

Output enable. Tri-states CLK2 when low. Internal pull-up.

10

GND

P

Connect to ground.

11

NO_INB

O

Goes high when clock on INB stops.

12

NO_INA

O

Goes high when clock on INA stops.

13

CLK2

O

Clock 2 Output. Low skew compared to CLK1.

14

CLK1

O

Clock 1 Output. Low skew compared to CLK2.

15

VDDC

P

Main chip supply. Output clocks amplitude will match this VDD.

16

OE1

I

Output Enable. Tri-states CLK1 when low. Internal pull-up.