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ICS570MT Datasheet(PDF) 3 Page - Integrated Circuit Systems |
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ICS570MT Datasheet(HTML) 3 Page - Integrated Circuit Systems |
3 / 6 page ICS570A Multiplier and Zero Delay Buffer MDS 570A C 3 Revision 102700 Printed 11/14/00 Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com Electrical Specifications Parameter Conditions Minimum Typical Maximum Units ABSOLUTE MAXIMUM RATINGS (Note 1) ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage, VDD Referenced to GND 7 V Inputs Referenced to GND -0.5 VDD+0.5 V Clock Output Referenced to GND -0.5 VDD+0.5 V Ambient Operating Temperature ICS570M 0 70 °C ICS570MI -40 85 °C Soldering Temperature Max of 10 seconds 260 °C Storage temperature -65 150 °C DC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted) DC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted) DC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted) Operating Voltage, VDD 3 5.5 V Input High Voltage, VIH, VDD=5V ICLK, FBIN 2 V Input Low Voltage, VIL, VDD=5V ICLK, FBIN 0.8 V Input High Voltage, VIH S0, S1 VDD-0.5 V Input High Voltage, VIM (mid-level) S0, S1 VDD/2 V Input Low Voltage, VIL S0, S1 0.5 V Output High Voltage, VOH, CMOS level IOH=-4mA VDD-0.4 V Output High Voltage, VOH IOH=-12mA 2.4 V Output Low Voltage, VOL IOL=12mA 0.4 V IDD Operating Supply Current, 50 in, 100 out No Load, 5.0V 22 mA IDD Operating Supply Current, 50 in, 100 out No Load, 3.3V 12 mA Short Circuit Current Each Output ±50 mA Input Capacitance, S1, S0 5 pF AC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted) AC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted) AC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted) Input Frequency, ICLK (see table on page 2) 2.5 150 MHz Output Clock Frequency, CLK 10 150 MHz Skew of output clocks Note 2 50 150 ps Input skew, ICLK to FBIN Note 2 VDD=3.3V, CLK>10MHz -500 500 ps Input skew, ICLK to FBIN Note 2 VDD=3.3V, CLK<5MHz -1.0 1.0 ns Input skew, ICLK to FBIN Note 2 VDD=3.3V, CLK<10MHz -750 750 ps Input skew, ICLK to FBIN Note 2 VDD=5V, CLK<10MHz -1.5 1.5 ns Input skew, ICLK to FBIN Note 2 VDD=5V, CLK>10MHz -1.0 1.0 ns Output Clock Rise Time, 3.3V 0.8 to 2.0V, note 3 0.75 ns Output Clock Fall Time, 3.3V 2.0 to 0.8V, note 3 0.75 ns Output Clock Rise Time, 5V 0.8 to 2.0V, note 3 0.5 ns Output Clock Fall Time, 5V 2.0 to 0.8V, note 3 0.5 ns Output Clock Duty Cycle at VDD/2 45 49 to 51 55 % Notes 1. Stresses beyond these can permanently damage the device 2. Assumes clocks with same rise time, measured from rising edges at VDD/2. 3. With 27 Ω terminating resistor and 15 pF loads. |
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