ICS581-01, -02

Zero-Delay Glitch-Free Clock Multiplexer

MDS 581-01, 581-02 A

3

Revision 041100

Printed 11/14/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

Device Operation

The ICS581-01 and ICS581-02 are very similar. The following describes the operation of the ICS581-01,

and then the differences of the ICS581-02 will be discussed.

The ICS581-01 is a PLL based, zero delay, clock multiplexer. The device consists of an input multiplexer

controlled by SELA that selects between 2 clock inputs. The output of the mux drives the reference input of

a phase-locked loop. The other input to the PLL comes from a feedback input pin called FBIN. The output

of the PLL drives 4 low skew outputs. These chip outputs are therefore buffered versions of the selected

input clock with zero delay and 50/50 duty cycle.

For correct operation, one of the clock outputs must be connected to FBIN. In this datasheet, CLK4 is

shown as the feedback, but any of the 4 clock outputs can be used. If output termination resistors are used,

the feedback should be connected after the resistor. It is a property of the PLL used on this chip that it will

align rising edges on FBIN and either INA or INB (depending on SELA). Since FBIN is connected to a

clock output, this means that the outputs appear to align with the input with zero delay.

When the input select (SELA) is changed, the output clock will change frequency and/or phase until it lines

up with the new input clock. This occurs in a smooth, gradual manner without any short pulses or glitches,

and will typically take a few tens of microseconds.

The part must be configured to operate in the correct frequency range. The Table on page 2 gives the

recommended range.

The 4 low skew outputs are controlled by 2 output enable pins that allow either 1, 3 or 4 simultaneous

outputs. If both OE pins are low, the PLL is powered down. Note that the clock driving the FBIN pin must

not be tri-stated unless the PLL is powered down, otherwise the PLL will run open loop.

The ICS581-02 is identical to the ICS581-01 except for the switching of the input mux. On the ICS581-

02, the switching is automatically controlled by a transition detector. The transition detector monitors the

clock on INA. If this clock stops, the output of the detector, NO_INA, goes high which then selects clock

input INB to the mux. The definition of the clock stopping is determined by a timeout selected by input

DIV. If DIV is low, NO_INA will go high after no transitions have occurred on INA for nominally 3 cycles

of the clock on INB. If DIV is high the timeout is nominally 48 cycles of INB. When INA restarts, the

mux immediately switches back to the INA selection with no timeout.

Input Clock Frequency

The ICS581-01 and 02 are designed to switch between 2 clocks of the same frequency. They will also

operate with different frequencies on each of the 2 input clocks. If the 2 input frequencies require different

input ranges, (table on page 2) then the highest range should be permanently selected. When the selected

input clock is outside this range, jitter and input skew specifications may not be met. Consult ICS for

more information.