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ICS85304-01 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS85304-01 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 13 page 85304AG-01 www.icst.com/products/hiperclocks.html REV. B JULY 13, 2001 1 Integrated Circuit Systems, Inc. ICS85304-01 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION The ICS85304-01 is a low skew, high perfor- mance 1-to-5 Differential-to-3.3V LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85304-01 has two selectable clock in- puts. The CLK, nCLK pair can accept most standard differen- tial input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally syn- chronized to eliminate runt clock pulses on the outputs dur- ing asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS85304-01 ideal for those applications demanding well defined performance and repeatability. FEATURES • 5 differential 3.3V LVPECL outputs • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 650MHz • Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 35ps (maximum) • Part-to-part skew: 150ps (maximum) • Propagation delay: 2.1ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC CLK_EN VCC nPCLK PCLK VEE nCLK CLK CLK_SEL VCC CLK nCLK PCLK nPCLK Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 0 1 CLK_EN CLK_SEL D Q LE HiPerClockS™ ,&6 ICS85304-01 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm Package Body G Package Top View 0 1 |
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