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ICS8701CYT Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS8701CYT Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 15 page  8701CY www.icst.com/products/hiperclocks.html REV. B AUGUST 2, 2001 1 Integrated Circuit Systems, Inc. ICS8701 LOW SKEW ÷1, ÷2 CLOCK GENERATOR GENERAL DESCRIPTION The ICS8701 is a low skew, ÷1, ÷2 Clock Gen- erator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The low impedance LVCMOS out- puts are designed to drive 50 Ω series or par- allel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. The divide select inputs, DIV_SELx, control the output fre- quency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/ OE, resets the internal frequency dividers and also con- trols the active and high impedance states of all outputs. The ICS8701 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701 ideal for those clock distribution applications de- manding well defined performance and repeatability. FEATURES • 20 LVCMOS outputs, 7 Ω typical output impedance • 1 LVCMOS clock input • Maximum output frequency up to 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications • Output skew: 250ps (maximum) • Part-to-part skew: 600ps (maximum) • Bank skew: 200ps (maximum) • Multiple frequency skew: 300ps (maximum) • 3.3V or mixed 3.3V input, 2.5V output operating supply modes • 0°C to 70°C ambient operating temperature • Other divide values available on request BLOCK DIAGRAM PIN ASSIGNMENT DIV_SELA DIV_SELB DIV_SELC DIV_SELD nMR/OE BANK_EN0 BANK_EN1 QAO - QA4 QB0 - QB4 QC0 - QC4 QD0 - QD4 CLK 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 QC3 VDDO QC4 QD0 VDDO QD1 GND QD2 GND QD3 VDDO QD4 QB1 VDDO QB0 QA4 VDDO QA3 GND QA2 GND QA1 VDDO QA0 48-Pin LQFP 7mm x 7mm x 1.4mm Y Package Top View ICS8701 HiPerClockS™ ,&6 1 0 ÷1 ÷2 1 0 1 0 1 0 Bank Enable Logic |
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