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ADV478 Datasheet(PDF) 9 Page - Analog Devices |
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ADV478 Datasheet(HTML) 9 Page - Analog Devices |
9 / 12 page ADV478/ADV471 –9– REV. B The contents of the pixel read mask register, which may be ac- cessed by the MPU at any time, are bit-wise logically ANDed with the P0–P7 inputs. Bit D0 of the pixel read mask register corresponds to pixel input P0. The addressed location provides 24 bits (18 bits for the ADV471) of color information to the three D/A converters. For additional information on Pixel Mask Register, see applica- tion note “Animation Using the Pixel Read Mask Register of the ADV47X Series of Video RAM-DACs” (Publication Number E1316–15–10/89). The SYNC and BLANK inputs, also latched on the rising edge of CLOCK to maintain synchronization with the color data, add appropriately weighted currents to the analog outputs, produc- ing the specific output levels required for video applications, as illustrated in Figures 3 and 4. Tables IV and V detail how the SYNC and BLANK inputs modify the output levels. The SETUP input is used to specify whether a 0 IRE (SETUP = GND) or 7.5 IRE (SETUP = VAA) blanking pedestal is to be used. The analog outputs of the ADV478 and ADV471 are capable of directly driving a 37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable. Figure 4. Composite Video Output Waveform (SETUP = GND) Table V. Video Output Truth Table (SETUP = GND) DAC Description IOUT (mA) l SYNC BLANK Input Data WHITE LEVEL 26.67 1 1 FFH DATA data+8.05 1 1 data DATA-SYNC data 0 1 data BLACK LEVEL 8.05 1 1 00H BLACK-SYNC 0 0 1 00H BLANK LEVEL 8.05 1 0 xxH SYNC LEVEL 0 0 0 xxH NOTE 1Typical with full-scale IOG= 26.67 mA, SETUP = GND. External voltage or current reference adjusted for 26.67 mA full-scale output. OBSOLETE |
Similar Part No. - ADV478_15 |
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Similar Description - ADV478_15 |
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