AD9772_15 datasheet(8/30 Pages) AD

Part #	AD9772

Description	14 BIT 150 MSPS T DAC WITH 2 INTERPOLATION FILTER

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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8 / 30 page

REV. 0

AD9772

–8–

DEFINITIONS OF SPECIFICATIONS

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual

analog output from the ideal output, determined by a straight

line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normal-

ized to full scale, associated with a 1 LSB change in digital input

code.

Monotonicity

A D/A converter is monotonic if the output either increases or

remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is

called offset error. For IOUTA, 0 mA output is expected when

the inputs are all 0s. For IOUTB, 0 mA output is expected

when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The

actual span is determined by the output when all inputs are set

to 1s, minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (+25

°C) value to the value at either T

MIN or TMAX.

For offset and gain drift, the drift is reported in ppm of full-

scale range (FSR) per degree C. For reference drift, the drift is

reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies

are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a

specified error band about its final value, measured from the

start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output

signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured fundamental. It is

expressed as a percentage or in decibels (dB).

Signal-to-Noise Ratio (SNR)

S/N is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the

Nyquist frequency, excluding the first six harmonics and dc.

The value for SNR is expressed in decibels.

Passband

Frequency band in which any input applied therein passes

unattenuated to the DAC output.

Stopband Rejection

The amount of attenuation of a frequency outside the passband

applied to the DAC, relative to a full-scale signal applied at the

DAC input within the passband.

Group Delay

Number of input clocks between an impulse applied at the

device input and peak DAC output current.

Impulse Response

Response of the device to an impulse applied to the input.

Adjacent Channel Power Ratio (or ACPR)

A ratio in dBc between the measured power within a channel

relative to its adjacent channel.

AD9772

3.0V

FROM HP8644A

SIGNAL GENERATOR

3.0V

CLKVDD

CLKCOM

CLK+

1

FILTER

CONTROL

MUX

CONTROL

PLLCOM

LPF

PLLVDD

IOUTA

IOUTB

REFIO

FSADJ

REFLO

AVDD

ACOM

DVDD

DCOM

SLEEP

EDGE-

TRIGGERED

LATCHES

ZERO

STUFF

MUX

14-BIT DAC

100

MINI-CIRCUITS

T1–1T

20pF

50

20pF

1.91k

0.1 F

+1.2V REFERENCE

AND CONTROL AMP

AWG2021

OR

DG2020

DIGITAL

DATA

EXT.

CLOCK

HP8130

PULSE GENERATOR

CH1

CH2

EXT. INPUT

PLLCLOCK

MULTIPLIER

2 /4

CLK–

1k

1 /2

CLOCK DISTRIBUTION

AND MODE SELECT

2

FIR

INTERPOLATION

FILTER

TO FSEA30

SPECTRUM

ANALYZER

Figure 3. Basic AC Characterization Test Setup

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