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IDT70125S Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT70125S Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 12 page 6.10 2 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE DESCRIPTION (Cont'd): Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 500mW of power. Low-power (L) versions offer battery backup data PIN CONFIGURATIONS (1,2) RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Ambient Temperature GND VCC Commercial 0 °C to +70°C 0V 5.0V ± 10% 2654 tbl 02 RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5 5.5 V GND Supply Voltage 0 0 0.0 V VIH Input High Voltage 2.2 – 6.0(2) V VIL Input Low Voltage –0.5 (1) – 0.8 V NOTES: 2654 tbl 03 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 0.5V. ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Commercial Unit VTERM (2) Terminal Voltage –0.5 to +7.0 V with Respect to GND TA Operating 0 to +70 °C Temperature TBIAS Temperature –55 to +125 °C Under Bias TSTG Storage –55 to +125 °C Temperature IOUT DC Output 50 mA Current NOTES: 2654 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.5V. retention capability with each port typically consuming 200 µW from a 2V battery. The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC. CAPACITANCE(1) (TA = +25 °C, f = 1.0MHz) Symbol Parameter Condition (2) Max. Unit CIN Input Capacitance VIN = 3dV 9 pF COUT Output Capacitance VOUT = 3dV 10 pF 2654 tbl 13 NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. This text does not indicate the orientation of the actual part-marking. A9R 8 9 10 11 12 13 14 15 16 17 18 IDT70121/125 J52-1 19 A6L A7L A1L A2L A3L A4L A5L A8L I/O0L I/O1L I/O2L I/O3L 46 45 44 43 42 41 40 39 38 37 36 35 A5R A6R A0R A1R A2R A3R A4R A7R A8R I/O8R I/O7R INDEX 34 20 OER A9L 2654 drw 02 PLCC TOP VIEW(3) NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. |
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