Electronic Components Datasheet Search |
|
IDT70125S Datasheet(PDF) 8 Page - Integrated Device Technology |
|
IDT70125S Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 12 page 6.10 8 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY BUSY BUSY BUSY BUSY (1,2,3) tAPS ADDR 'A' DATAIN 'A' MATCH tWC tWP R/ W'A' ADDR'B' DATAOUT 'B' MATCH BUSY'B' tBDA tDW tDH VALID VALID tDDD (4) tWDD tBDD 2654 drw 09 (1) TIMING WAVEFORM OF WRITE WITH BUSY BUSY BUSY BUSY BUSY NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High. 3. All timing is the same for left and right ports. Port 'A' may be either left or right port. Port 'B' is the opposite from port 'A'. 2654 drw 10 R/ W'A' BUSY'B' tWP tWB R/ W'B' tWH (1) (2) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT 70125). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'. |
Similar Part No. - IDT70125S |
|
Similar Description - IDT70125S |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |