6.13

10

IDT7016S/L

HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

W

W

W

W

R/

W

(2)

OE

ADDRESS

CE or SEM

(6)

(4)

(4)

(3)

3190 drw 09

(7)

(9)

(7)

NOTES:

1. R/

W or CE must be High during all address transitions.

CE and a Low R/W for memory array writing cycle.

CE or R/W (or SEM or R/W) going High to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the

CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last,

CE or R/W.

7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured +/-200mV from steady state with the Output

Test load (Figure 2).

8. If

OE is high during an R/W controlled write cycle, this requirement does not apply and the write pulse can

9. To access RAM,

3190 drw 10

ADDRESS

CE or SEM

R/

W

(3)

(2)

(6)

(9)

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

CE

CE

CE

CE