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IDT7025L Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7025L Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 20 page  IDT7025S/L HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.16 7 IDT7025X35 IDT7025X55 IDT7025X70 Mil. Only Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 — 55 — 70 — ns tAA Address Access Time — 35 — 55 — 70 ns tACE Chip Enable Access Time (3) —35—55 —70 ns tABE Byte Enable Access Time (3) —35—55 —70 ns tAOE Output Enable Access Time — 20 — 30 — 35 ns tOH Output Hold from Address Change 3 — 3 — 3 — ns tLZ Output Low-Z Time (1, 2) 3— 3— 3— ns tHZ Output High-Z Time (1, 2) —15—25 —30 ns tPU Chip Enable to Power Up Time (1,2) 0— 0— 0— ns tPD Chip Disable to Power Down Time (1,2) —35—50 —50 ns tSOP Semaphore Flag Update Pulse ( OE or SEM) 15—15 —15— ns tSAA Semaphore Address Access Time (3) —35—55 —70 ns NOTES: 2683 tbl 13 1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semephore, CE = VIH or UB & LB = VIH, and SEM = VIL. 4. "X" in part numbers indicates power rating (S or L). AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4) IDT7025X15 IDT7025X17 IDT7025X20 IDT7025X25 Com'l. Only Com'l. Only Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 — 17 — 20 — 25 — ns tAA Address Access Time — 15 — 17 — 20 — 25 ns tACE Chip Enable Access Time (3) — 15 — 17 — 20 — 25 ns tABE Byte Enable Access Time (3) — 15 — 17 — 20 — 25 ns tAOE Output Enable Access Time — 10 — 10 — 12 — 13 ns tOH Output Hold from Address Change 3 — 3 — 3 — 3 — ns tLZ Output Low-Z Time (1, 2) 3 — 3 — 3 — 3 — ns tHZ Output High-Z Time (1, 2) — 10 — 10 — 12 — 15 ns tPU Chip Enable to Power Up Time (1,2) 0 — 0 — 0 — 0 — ns tPD Chip Disable to Power Down Time (1,2) — 15 — 17 — 20 — 25 ns tSOP Semaphore Flag Update Pulse ( OE or SEM) 10 — 10 — 10 — 10 — ns tSAA Semaphore Address Access (3) — 15 — 17 — 20 — 25 ns AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 2683 tbl 12 Figure 1. AC Output Test Load Figure 2. Output Test Load ( for tLZ, tHZ, tWZ, tOW) * including scope and jig. 2683 drw 06 1250 Ω 30pF 775 Ω 5V DATAOUT BUSY INT 1250 Ω 5pF 775 Ω 5V DATAOUT |
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