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IDT49C460DFF Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT49C460DFF Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 32 page  11.6 9 IDT49C460/A/B/C/D/E 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT MILITARY AND COMMERCIAL TEMPERATURE RANGES 32-BIT DATA WORD CONFIGURATION A single IDT49C460 EDC unit, connected as shown in Figure 1, provides all the logic needed for single bit error correction and double bit error detection of a 32-bit data field. The identification code indicates 7 check bits are required. The CB7 pin should be HIGH. Figure 3 indicates the 39-bit data format for two bytes of data and 7 check bits. Table 3 describes the operating mode available. Table 6 indicates the data bits participating in the check bit generation. For example, check bit C0 is the exclusive-OR function of the 16 data input bits marked with an X. Check bits are generated and output in the Generate and Initialization Mode. Check bits from the respective latch are passed, unchanged, in the PASSTHRU or Diagnostic Generate Mode. Syndrome bits are generated by an exclusive-OR or the generated check bits with the read check bits. For example, Sn is the XOR of check bits Cn from those read with those generated. Table 7 indicates the decoding of the seven syndrome bits to identify the bit-in-error for a single bit error, or whether a double or triple bit error was detected. The all zero case indicates no errors detected. In the Correct Mode, the syndrome bits are used to complement (correct) single bit errors in the data bits. For double or multiple error detection, the data available as input to the Data Out Latch is not defined. Table 5 defines the bit definition for the Diagnostic Latch. As defined in Table 3, several modes will use the diagnostic check bits to determine syndrome bits or to pass as check bits to the SC0–7 outputs. The Internal Mode substitutes the indicated bit position for the external control signals. 2584 drw 05 Table 5. 32-Bit Diagnostic Latch Coding Format BIT 0 CB0 DIAGNOSTIC BIT 1 CB1 DIAGNOSTIC BIT 2 CB2 DIAGNOSTIC BIT 3 CB3 DIAGNOSTIC BIT 4 CB4 DIAGNOSTIC BIT 5 CB5 DIAGNOSTIC BIT 6 CB6 DIAGNOSTIC BIT 7 CB7 DIAGNOSTIC BIT 8 CODE ID0 BIT 9 CODE ID1 BIT 10 DIAG MODE0 BIT 11 DIAG MODE1 BIT 12 CORRECT BIT 13–31 DON'T CARE Generated Participating Data Bits Check Bits Parity 0123456 789 10 11 12 13 14 15 C0 Even (XOR) X X X X X X X X C1 Even (XOR) X X X X X X X X C2 Odd (XNOR) X X X X X X X X C3 Odd (XNOR) X X X X X X X X C4 Even (XOR) X X X X X X X X C5 Even (XOR) X X X X X X X X C6 Even (XOR) XXXX X XXX 2584 tbl 06 Table 6. 32–Bit Modified Hamming Code–Check Bit Encode Chart 2584 tbl 07 Generated Participating Data Bits Check Bits Parity 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 C0 Even (XOR) X X X X X X X X C1 Even (XOR) X X X X X X X X C2 Odd (XNOR) X X X X X X X X C3 Odd (XNOR) X X X X X X X X C4 Even (XOR) X X X X X X X X C5 Even (XOR) X X X X X X X X C6 Even (XOR) X X X X X X X X |
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