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IDT70125S35J Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT70125S35J Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 12 page  6.10 7 IDT 70121/70125S/L HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6) 70121X25 70121X35 70121X45 70121X55 70125X25 70125X35 70125X45 70125X55 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit Busy Timing (For Master IDT70121 Only) tBAA BUSY Access Time from Address — 20 — 20 — 20 — 30 ns tBDA BUSY Disable Time from Address — 20 — 20 — 20 — 30 ns tBAC BUSY Access Time from Chip Enable — 20 — 20 — 20 — 30 ns tBDC BUSY Disable Time from Chip Enable — 20 — 20 — 20 — 30 ns tWDD Write Pulse to Data Delay (1) —50— 60 —70—80 ns tDDD Write Data Valid to Read Data Delay (1) —35— 45 —55—65 ns tAPS Arbitration Priority Set-up Time (2) 5— 5 — 5— 5— ns tBDD BUSY Disable to Valid Data(3) —30— 30 —35—45 ns tWH Write Hold After BUSY(5) 15 — 20 — 20 — 20 — ns Busy Timing (For Slave IDT70125 Only) tWB Write to BUSY Input(4) 0— 0 — 0— 0— ns tWH Write Hold After BUSY (5) 15 — 20 — 20 — 20 — ns tWDD Write Pulse to Data Delay (1) —50— 60 —70—80 ns tDDD Write Data Valid to Read Data Delay (1) —35— 45 —55—65 ns NOTES: 2654 tbl 10 1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY“. 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.. 5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 6. “X” in part numbers indicates power rating (S or L). NOTES: 1. R/ W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL 3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal ( CE or R/W) is asserted last. 7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CE CE CE CE CONTROLLED TIMING(1,5) CE tWC tAS tWR tDW tDH ADDRESS DATAIN R/ W tAW tEW 2654 drw 08 (6) (2) (3) |
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