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IDT70825L Datasheet(PDF) 11 Page - Integrated Device Technology

Part # IDT70825L
Description  HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM??
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70825L Datasheet(HTML) 11 Page - Integrated Device Technology

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IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.31
11
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (2,3)
IDT70825X20
IDT70825X25
IDT70825X35
IDT70825X45
Com'l. Only
Com'l. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
25
35
45
ns
tAA
Address Access Time
20
25
35
45
ns
tACE
Chip Enable Access Time
20
25
35
45
ns
tBE
Byte Enable Access Time
20
25
35
45
ns
tOE
Output Enable Access Time
10
10
15
20
ns
tOH
Output Hold from Address Change
3
3
3
3
ns
tCLZ
Chip Select Low-Z Time(1)
3
3—
3—
3—
ns
tBLZ
Byte Enable Low-Z Time(1)
3
3—
3—
3—
ns
tOLZ
Output Enable Low-Z Time(1)
2
2—
2—
2—
ns
tCHZ
Chip Select High-Z Time(1)
10
12
15
15
ns
tBHZ
Byte Enable High-Z Time(1)
10
12
15
15
ns
tOHZ
Output Enable High-Z Time(1)
9
—11—15
—15
ns
tPU
Chip Select Power-Up Time
0
0
0
0
ns
tPD
Chip Select Power-Down Time
20
25
35
45
ns
NOTES:
1. Transition measured at
±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3.
CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (2,4)
IDT70825X20
IDT70825X25
IDT70825X35
IDT70825X45
Com'l. Only
Com'l. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
20
25
35
45
ns
tCW
Chip Select to End-of-Write
15
20
25
30
ns
tAW
Address Valid to End-of-Write(3)
15
20
25
30
ns
tAS
Address Set-up Time
0
0
0
0
ns
tWP
Write Pulse Width(3)
13
20
25
30
ns
tBP
Byte Enable Pulse Width(3)
15
20
25
30
ns
tWR
Write Recovery Time
0
0
0
0
ns
tWHZ
Write Enable Output High-Z Time(1)
—10—12
—15—15
ns
tDW
Data Set-up Time
13
15
20
25
ns
tDH
Data Hold Time
0
0
0
0
ns
tOW
Output Active from End-of-Write
3
3
3
3
ns
NOTES:
1. Transition measured at
±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3.
OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and on the data to be placed on the bus for the required tDW. If
OE is HIGH during the R/W controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the
CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4.
CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
3016 tbl 21
3016 tbl 20
CASES 8 AND 9: (RESERVED)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.


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