Electronic Components Datasheet Search |
|
IDT7026S35G Datasheet(PDF) 8 Page - Integrated Device Technology |
|
IDT7026S35G Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 18 page 6.17 8 IDT7026S/L HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. WAVEFORM OF READ CYCLES(5) tRC R/ W CE ADDR tAA OE UB, LB 2939 drw 06 (4) tACE (4) tAOE (4) tABE (4) (1) tLZ tOH (2) tHZ (3, 4) tBDD DATAOUT BUSYOUT VALID DATA (4) TIMING OF POWER-UP POWER-DOWN CE 2939 drw 07 tPU ICC ISB tPD 50% 50% |
Similar Part No. - IDT7026S35G |
|
Similar Description - IDT7026S35G |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |