6.31

8

IDT70825S/L

HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Inputs/Outputs

SCLK

SLD

SLD

SLD

SLD

SLD SSTRT

SSTRT

SSTRT

SSTRT

SSTRT

SSTRT

SSTRT

SOE

SOE

SOE

SOE

MODE

H

L

H

X

Start address for Buffer #1 loaded into Address Pointer.

H

H

L

X

Start address for Buffer #2 loaded into Address Pointer.

LH

H

NOTES:

3016 tbl 14

2.

RST is continuously HIGH. The conditions of SCE, CNTEN, and SR/W are unrelated to the sequential address pointer operations.

3.

the sequential port operation (due to the counter and register control).

4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.

5. When

SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address

is not incremented during the two cycles.

6.

SOE may be LOW with SCE deselect or in the write mode using SR/W.

ADDRESS POINTER LOAD CONTROL (SLD)

In

SLD mode, there is an internal delay of one cycle before

the address pointer changes in the cycle following

SLD. When

data-in register on the LOW-to-HIGH transition of

SCLK. On

the cycle following

SLD, the address pointer changes to the

address location contained in the data-in register.

following

clock cycle, since these addresses are pre-loaded in the

registers already.

NOTE:

address pointer changes). At SCLK edge (A),

(B),

for edge (B), while data will not be ready at edge (B) when

SLD is used, but will be ready at edge (C).

15

MSB

LSB SI/O BITS

H

3016 drw 09

HH

H

12 ------------------------------------------------------------------------------------------------------------

Address Loaded into Pointer

0

14

13

NOTE:

SLD

SCLK

A

B

3016 drw 08

C

(1)

SLD

SLD

SLD

SLD