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IDT70825S35PF Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT70825S35PF Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 21 page  IDT70825S/L HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.31 7 TRUTH TABLE II – SEQUENTIAL READ (1,2,3,6,8) Inputs/Outputs MODE SCLK SCE SCE SCE SCE SCE CNTEN CNTEN CNTEN CNTEN CNTEN SR/W W W W W EOB1 EOB1 EOB1 EOB1 EOB1 EOB2 EOB2 EOB2 EOB2 EOB2 SOE SOE SOE SOE SOE SI/O L L H LOW LAST L [EOB1] Counter Advanced Sequential Read with EOB1 reached. L H H LAST LAST L [EOB1 - 1] Non-Counter Advanced Sequential Read, without EOB1 reached. L L H LAST LOW L [EOB2] Counter Advanced Sequential Read with EOB2 reached. L H H LAST LAST L [EOB2 - 1] Non-Counter Advanced Sequential Read without EOB2 reached. L L H LOW LOW H HIGH-Z Counter Advanced Sequential Non-Read with EOB1 and EOB2 reached. 3016 tbl 11 3016 tbl 12 TRUTH TABLE I – RANDOM ACCESS READ AND WRITE (1,2) Inputs/Outputs MODE CE CE CE CE CE CMD CMD CMD CMD CMD R/W W W W W OE OE OE OE OE LB LB LB LB LB UB UB UB UB UB I/O0-I/O7 I/O8-I/O- L H H L L L DATAOUT DATAOUT Read both Bytes. L H H L L H DATAOUT High-Z Read lower Byte only. L H H L H L High-Z DATAOUT Read upper Byte only. LH L H(3) L L DATAIN DATAIN Write to both Bytes. LH L H(3) L H DATAIN High-Z Write to lower Byte only. LH L H(3) H L High-Z DATAIN Write to upper Byte only. H H X X X X High-Z High-Z Both Bytes deselected and powered down. L H H H X X High-Z High-Z Outputs disabled but not powered down. L H X X H H High-Z High-Z Both Bytes deselected but not powered down. HL L H(3) L(4) L(4) DATAIN DATAIN Write I/O0-I/O12 to the Buffer Command Register. HL H L L(4) L(4) DATAOUT DATAOUT Read contents of the Buffer Command Register via I/O0-I/O12. NOTES: 1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. 2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and operation. 3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven. 4. Byte operations to control register using UB and LB separately are also allowed. TRUTH TABLE III – SEQUENTIAL WRITE (1,2,3,4,5,6,7,8) Inputs/Outputs MODE SCLK SCE SCE SCE SCE SCE CNTEN CNTEN CNTEN CNTEN CNTEN SR/W W W W W EOB1 EOB1 EOB1 EOB1 EOB1 EOB2 EOB2 EOB2 EOB2 EOB2 SOE SOE SOE SOE SOE SI/O L H L LAST LAST H SI/OIN Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached L L L LOW LOW H SI/OIN Counter Advanced Sequential Write with EOB1 and EOB2 reached. H H X LAST LAST X High-Z No Write or Read due to Sequential port Deselect. No counter advance. H L X NEXT NEXT X High-Z No Write or Read due to Sequential port Deselect. Conter does advance. NOTES: 1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. LOW = VOL. 2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations. 3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access. 4. SOE must be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising edge of the clock during the cycle in which SR/ W = VIL. 5. SI/OIN refers to SI/O0-SI/O15 inputs. 6. "LAST" refers to the previous value still being output, no change. 7. Termination of a write is done on the Low-to-High transition of SCLK if SR/ W or SCE is High. 8. When CLKEN=Low, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter Enable Cycle after Reset, Read (and write) Cycle". 3016 tbl 13 |
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