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IDT70825S20G Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT70825S20G Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 21 page IDT70825S/L HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.31 5 3016 tbl 08 DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%) 70825X20 70825X25 70825X35 70825X45 Test Com'l. Only Com'l. Only Symbol Parameter Condition Version Typ.(2) Max. Typ.(2)Max. Typ.(2) Max. Typ.(2) Max. Unit ICC Dynamic Operating CE = VIL, Outputs MIL. S — — — — 160 400 155 400 mA Current Open, SCE = VIL(5) L — — — — 160 340 155 340 (Both Ports Active) f = fMAX(3) COM’L. S 180 380 170 360 160 340 155 340 L 180 330 170 310 160 290 155 290 ISB1 Standby Current SCE and CE > VIH(7) MIL. S — — — — 20 85 16 85 mA (Both Ports - TTL Level CMD = VIH L— — — — 20 65 16 65 Inputs) f = fMAX(3) COM’L. S 25 70 25 70 20 70 16 70 L 25 5025 50 2050 16 50 ISB2 Standby Current CE or SCE = VIH MIL. S — — — — 95 290 90 290 mA (One Port - TTL Level Active Port Outputs L —— — — 95 250 90 250 Input) Open, f = fMAX(3) COM’L. S 115 260 105 250 95 240 90 240 L 115 230 105 220 95 210 90 210 ISB3 Full Standby Current Both Ports CE and MIL. S — — — — 1.0 30 1.0 30 mA (Both Ports - CMOS SCE ≥ VCC - 0.2V(6,7) L — — — — 0.2 10 0.2 10 Level Inputs) VIN ≥ VCC - 0.2V or COM’L. S 1.0 15 1.0 15 1.0 15 1.0 15 VIN ≤ 0.2V, f = 0(4) L 0.2 5 0.2 5 0.2 5 0.2 5 ISB4 Full Standby Current One Port CE or MIL. S — — — — 90 260 85 260 mA (One Port - CMOS SCE ≥ VCC - 0.2V(6) L — — — — 90 215 85 215 Level Inputs) Outputs Open (Active port), f = fMAX(3) COM’L. S 110 240 100 230 90 220 85 220 VIN ≥ VCC - 0.2V or VIN ≤ 0.2V L 110 200 100 190 90 180 85 180 NOTES: 1. "X" in part number indicates power rating (S or L). 2. VCC = 5V, Ta = +25 °C; guaranteed by device characterization but not production tested. 3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC. 4. f = 0 means no address or control lines change. 5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK. 6. SCE may be ≤ 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown. 7. If one port is enabled (either CE or SCE = Low) then the other port is disabled (SCE or CE = High, respectively). CMOS High > Vcc - 0.2V and Low < 0.2V, and TTL High = VIH and Low = VIL. DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L VERSION ONLY) (VLC < 0.2V, VHC > VCC - 0.2V) Symbol Parameter Test Condition Min. Typ.(1) Max. Unit VDR VCC for Data Retention VCC = 2V 2.0 — — V ICCDR Data Retention Current CE = VHC MIL. — 100 4000 µA VIN = VHC or = VLC COM’L. — 100 1500 tCDR(3) Chip Deselect to Data Retention Time SCE = VHC(4) when SCLK= 0 — — ns tR(3) Operation Recovery Time CMD = VHC tRC(2) —— ns NOTES : 1. TA = +25 °C, VCC = 2V; guaranteed by device characterization but not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by device characterization, but is not production tested. 4. To initiate data retention, SCE = VIH must be clocked in. 3016 tbl 09 |
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