7.1

2

IDT29FCT52A/B/C, IDT29FCT53A/B/C

FAST CMOS OCTAL REGISTERED TRANSCEIVERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Name

I/O

Description

I/O

Eight bidirectional lines carrying the A Register inputs or B Register outputs.

I/O

Eight bidirectional lines carrying the B Register inputs or A Register outputs.

CPA

I

Clock for the A Register. When

CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition

of the CPA signal.

CEA

I

Clock Enable for the A Register. When

CEA is LOW, data is entered into the A Register on the LOW-to-HIGH

transition of the CPA signal. When

CEA is HIGH, the A Register holds its contents, regardless of CPA signal

transitions.

OEB

I

Output Enable for the A Register. When

CPB

I

Clock for the B Register. When

CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition

of the CPB signal.

CEB

I

Clock Enable for the B Register. When

CEB is LOW, data is entered into the B Register on the LOW-to-HIGH

transition of the CPB signal. When

CEB is HIGH, the B Register holds its contents, regardless of CPB signal

transitions.

OEA

I

Output Enable for the B Register. When

2533 tbl 01

PIN CONFIGURATIONS

DIP/CERPACK/SOIC

TOP VIEW

5

6

7

8

9

10

11

12

GND

1

2

3

4

24

23

22

21

20

19

18

17

Vcc

16

15

14

13

P24-1,

D24-1,

E24-1

&

SO24-2

CEB

CEA

CPB

CPA

OEA

B

0

OEB

REGISTER FUNCTION TABLE

(1)

(Applies to A or B Register)

Inputs

Internal

DCP

CE

CE

Q

Function

X

X

H

NC

Hold Data

L

↑

L

L

Load Data

H

↑

LH

2533 tbl 02

OUTPUT CONTROL

(1)

Internal

Y-Outputs

OE

OE

Q

52

53

Function

H

X

Z

Z

Disable Outputs

L

L

L

H

Enable Outputs

LH

HL

NOTE:

2533 tbl 03

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

NC = No Change

↑ = LOW-to-HIGH Transition

5

6

7

8

9

10

11

L28-1

25

24

23

22

21

20

19

INDEX

OEB

NC

NC

12 13 14 15 16 17 18

43

2

1

28 27 26

LCC

TOP VIEW

2533 drw 02