IDT70825S/L

HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY

MILITARY AND COMMERCIAL TEMPERATURE RANGES

6.31

3

SYMBOL

NAME

DESCRIPTION

SI/O0-15 Inputs

I/O

Sequential data inputs/outputs for 16-bit wide data.

SCLK

Clock

I

SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK.

Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH

transition of SCLK when

CNTEN is LOW.

SCE

Chip Enable

I

When

SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of

SCLK. When

SCE is HIGH, the sequential access port is disabled into powered-down mode on

the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the high-impedance state. All

data is retained, unless altered by the random access port.

CNTEN

Counter Enable

I

When

CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK.

This function is independant of

SCE.

SR/

W

Read/Write Enable

I

When SR/

W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of

SCLK. When SR/

W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the

LOW-to-HIGH transition of SCLK. Termination of a Write cycle is done on the Low-to-High

transistion of SCLK if SR/

W or SCE is High.

SLD

Address Pointer

I

When

SLD is sampled LOW, there is an internal delay of one cycle before the address pointer

Load Control

changes. When

on the LOW-to-HIGH transition of SCLK. On the cycle following

SLD, the address pointer

changes to the address location contained in the data-in register.

not be LOW while

SLD is LOW or during the cycle following SLD.

SSTRT1, Load Start of

I

When

SSTRT2

Address Register

address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in

internal registers.

following

SLD.

EOB1,

End of Buffer Flag

O

EOB2

stored in the end of buffer registers. The flags can be cleared by either asserting

RST LOW or

by writing zero into bit 0 and/or bit 1 of the control register at address 101.

dependent on separate internal registers, and therefore separate match addresses.

SOE

Output Enable

I

SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers

and the sequentially addressed data is output. When

SOE is HIGH, the SI/O output bus is in

the high-impedance state.

SOE is asynchronous to SCLK.

RST

Reset

I

When

RST is LOW, all internal registers are set to their default state, the address pointer is set

to zero and the

3016 tbl 02

SYMBOL

NAME

DESCRIPTION

Address Lines

I

Address inputs to access the 8192-word (16 bit) memory array.

I

Random access data inputs/outputs for 16-bit wide data.

CE

Chip Enable

I

When

CE is LOW, the random access port is enabled. When CE is HIGH, the random access

port is disabled into power-down mode and the I/O outputs are in the high-impedance state. All

data is retained during

CE = VIH, unless it is altered by the sequential port. CE and CMD may not

be LOW at the same time.

CMD

Control Register

I

When

Enable

access the control register, the flag register, and the start and end of buffer registers.

CMD and

CE may not be LOW at the same time.

R/

W

Read/Write Enable

I

If

CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the

array when R/

W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer com-

mand registers.

CE and CMD may not be LOW at the same time.

OE

Output Enable

I

When

OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O

outputs are in the high-impedance state.

LB,UB

Lower Byte, Upper

I

When

Byte Enables

UB controls access for I/O8-

LB.

Power Supply

GND

Ground

Ten Ground pins. All Ground pins must be connected to the same Ground supply.

3016 tbl 01

PIN DESCRIPTIONS: RANDOM ACCESS PORT

PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT

NOTE:

1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.