10

IDT70824S/L

High-Speed 4K x 16 Sequential Access Random Access Memory

Military and Commercial Temperature Ranges

End of buffer flag for Buffer #1

End of buffer flag for Buffer #2

15

0

MSB

H

HH

H

H

H

H

H

H

HH

H

H

1

0

LSB I/O BITS

H

3099 drw 12

Cases 8 and 9: (Reserved)

Illegal operations. All outputs will be HIGH on the I/O bus during a READ.

Case 7: Flag Status Register Read

Conditions

NOTES:

2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs asynchronously

of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled by

CNTEN. The pointer is

also released by

NOTE:

NOTES:

1.

2.

CMD flow control bits are unchanged, the count does not continue advancement.

3. If

4. If the counter has stopped at

EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK; otherwise the flow

control will remain in the stop mode.

5. Flow Control Bit settings of '10' and '11' are reserved.

6. Start address and End of address for Buffer #2 and the Flow Control for both Buffer #1 and #2, must be programmed as described in the "Buffer Command Mode"

section.

RST conditions are not set to valid addresses.

Cases 6: Flag Status Register

NOTES:

1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be

cleared while the second is left alone, or both may be cleared.

2. Remains as it was prior to the

CMD operation, either HIGH (1) or LOW (0).

Buffer #1 flow control

Buffer #2 flow control

Counter Release

(STOP Mode Only)

15

MSB

LSB I/O BITS

0

H

HH

H

H

HH

4

3

2

1

0

HH

H

H

3099 drw 11

Flow Control

Bit 1 & Bit 0

(Bit 3 & Bit 2)

Mode

Functional Description

00

BUFFER

CHAINING

The pointer value is changed to the start address of Buffer #2 (Buffer #1)

(1,3)

01

STOP

The address pointer will stop incrementing when it reaches the next address

(EOB address + 1), if CNTEN is LOW

on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on

EOB. Sequential write

operations are inhibited after the address pointer is stopped. The pointer can be released by bit 4 of the flow

control register.

(1,2,4)

3099 tbl 17

Flag Status Bit 0, (Bit 1)

Functional Description

0

Clears Buffer Flag

1

3099 tbl 18

Flag Status Bit 0, (Bit 1)

Functional Description

0

Pointer has not reached the End of the

Buffer.

1

Pointer has reached the end of the

Buffer.

3099 tbl 19