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IDT7027S55GB Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7027S55GB Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 19 page  ©2000 Integrated Device Technology, Inc. MAY 2000 DSC 3199/7 1 Functional Block Diagram Features x x x x x True Dual-Ported memory cells which allow simultaneous access of the same memory location x x x x x High-speed access – Military: 25/35/55ns (max) – Industrial: 25ns (max.) – Commercial: 20/25/35/55ns (max.) x x x x x Low-power operation – IDT7027S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7027L Active: 750mW (typ.) Standby: 1mW (typ.) x x x x x Separate upper-byte and lower-byte control for bus matching capability. x x x x x Dual chip enables allow for depth expansion without HIGH-SPEED 32K x 16 DUAL-PORT STATIC RAM IDT7027S/L external logic x x x x x IDT7027 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device x x x x x M/ S = VIH for BUSY output flag on Master, M/ S = VIL for BUSY input on Slave x x x x x Busy and Interrupt Flags x x x x x On-chip port arbitration logic x x x x x Full on-chip hardware support of semaphore signaling between ports x x x x x Fully asynchronous operation from either port x x x x x TTL-compatible, single 5V (±10%) power supply x x x x x Available in 100-pin Thin Quad Flatpack (TQFP) and 108-pin Ceramic Pin Grid Array (PGA) x x x x x Industrial temperature range (–40°C to +85°C) is available for selected speeds NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). I/O Control Address Decoder 32Kx16 MEMORY ARRAY 7027 ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0L OEL R/WL A14L A0L A14L A0L SEML INT L (2) BUSYL (1,2) LBL CE0L OEL UBL I/O Control Address Decoder CE0R OER R/ WR A14R A0R A14R A0R SEMR INTR (2) BUSYR (1,2) LBR R/WR OER UBR M/ S (2) CE1L CE0R CE1R 3199 drw 01 I/O CE1R CE1L 8-15L I/O I/O0-7R I/O8-15R 0-7L R/ WL . |
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