IDT7188L35DB datasheet(5/8 Pages) IDT

Part #	IDT7188L35DB

Description	CMOS STATIC RAM 64K 16K x 4-BIT

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Manufacturer	IDT [Integrated Device Technology]

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6.42

IDT7188S/L

CMOS Static RAM 64K (16K x 4-Bit)

Military Temperature Range

5

Timing Waveform of Read Cycle No. 2(1,3)

NOTES:

1.

WE is HIGH for Read cycle.

2.

CS is LOW for Read cycle.

3. Address valid prior to or coincident with

CS transition LOW.

4. Transition is measured ±200mV from steady state voltage.

5. All Read cycle timings are referenced from the last valid address to the first transitioning address.

Timing Waveform of Read Cycle No. 1(1,2)

AC Electrical Characteristics (VCC = 5.0V ± 10%)

ADDRESS

DATAOUT

2989 drw 06

tRC

tAA

tOH

PREVIOUS DATA VALID

DATA VALID

(5)

,

DATAOUT

CS

ICC

ISB

VCC SUPPLY

CURRENT

2989 drw 07

tACS

(4)

tLZ

(4)

tHZ

tPD

tPU

(5)

tRC

DATA VALID

HIGH IMPEDANCE

,

NOTE:

1. This parameter is guaranteed by device characterization but is not production tested.

Symbol

Parameter

7188S25

7188L25

7188S35

7188L35

7188S45

7188L45

7188S55

7188L55

7188S70

7188L70

7188S85

7188L85

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Read Cycle

tRC

Read Cycle Time

25

____

35

—

45

—

55

____

70

____

85

____

ns

tAA

Address Access Time

____

25

____

35

____

45

____

55

____

70

____

85

ns

tACS

Chip Select Access Time

____

25

____

35

____

45

____

55

____

70

____

85

ns

tOH

Output Hold from Address Change

5

____

5

____

5

____

5

____

5

____

5

____

ns

tLZ

(1)

Output Select to Output in Low-Z

5

____

5

____

5

____

5

____

5

____

5

____

ns

tHZ

(1)

Chip Deselect to Output in High-Z

____

10

____

14

____

14

____

20

____

25

____

30

ns

tPU

(1)

Chip Select to Power Up Time

0

____

0

____

0

____

0

____

0

____

0

____

ns

tPD

(1)

Chip Deselect to Power Down Time

____

25

____

35

____

45

____

55

____

70

____

85

ns

2989 tbl 11

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