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IDT71B74S12TP Datasheet(PDF) 2 Page - Integrated Device Technology

Part # IDT71B74S12TP
Description  BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
Download  9 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT71B74S12TP Datasheet(HTML) 2 Page - Integrated Device Technology

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IDT71B74
BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
14.1
2
PIN CONFIGURATION
TRUTH TABLE
(1, 2)
WE
WE CS
CS OE
OE RESET
RESET MATCH I/O
Function
X
X
X
L
HIGH
Reset all bits to LOW
X
H
X
H
HIGH
Hi-Z
Deselect chip
H
L
H
H
LOW
DIN
No MATCH
H
L
H
H
HIGH
DIN
MATCH
H
L
L
H
HIGH
DOUT
Read
L
L
X
H
HIGH
DIN
Write
NOTES:
3013 tbl 01
1. H = VIH, L = VIL, X = DON'T CARE
2. HIGH = High-Z (pulled up by an external resistor), and LOW = VOL.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Com’l.
Unit
VTERM
(2)
Terminal Voltage with
–0.5 to +7.0
V
Respect to GND
TA
Operating Temperature
0 to +70
°C
TBIAS
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–55 to +125
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
NOTES:
3013 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
DIP/SOJ
TOP VIEW
3013 drw 02
5
6
7
8
9
10
11
12
1
2
3
4
24
23
22
21
20
19
18
17
P28-2
SO28-5
13
14
28
27
26
25
A7
A6
A5
A4
A3
A2
A1
A0
I/O 0
I/O 1
VCC
A8
A9
A11
A10
I/O 7
WE
OE
CS
16
15
I/O 2
GND
I/O 6
I/O 5
I/O 4
I/O 3
A12
RESET
MATCH
CAPACITANCE
(TA = +25
°C, f = 1.0MHz, SOJ Package)
Symbol
Parameter
(1)
Conditions
Max. Unit
CIN
Input Capacitance
VIN = 3dV
6
pF
COUT
Output Capacitance
VOUT = 3dV
7
pF
NOTE:
3013 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
PIN DESCRIPTIONS
Pin Names
Description
A012
Address
I/O0-7
Data Input/Output
CS
Chip Select
RESET
Memory Reset
MATCH
Data/Memory Match (Open Drain)
WE
Write Enable
OE
Output Enable
GND
Ground
VCC
Power
3013 tbl 02


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