5

IDT71L016

LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

71L016L70

71L016L100

Symbol

Parameter

Min.

Max.

Min.

Max.

Units

Read Cycle

Read Cycle Time

70

—

100

—

ns

Address Access Time

—

70

—

100

ns

Chip Select Access Time

—

70

—

100

ns

(1)

Chip Select Low to Output in Low-Z

10

—

10

—

ns

(1)

Chip Select High to Output in High-Z

—

25

—

30

ns

Output Enable Low to Output Valid

—

35

—

50

ns

(1)

Output Enable Low to Output in Low-Z

5

—

5

—

ns

(1)

Output Enable High to Output in High-Z

—

25

—

30

ns

Output Hold from Address Change

10

—

15

—

ns

Byte Enable Low to Output Valid

—

35

—

50

ns

(1)

Byte Enable Low to Output in Low-Z

5

—

5

—

ns

(1)

Byte Enable High to Output in High-Z

—

25

—

30

ns

Write Cycle

Write Cycle Time

70

—

100

—

ns

Address Valid to End of Write

65

—

80

—

ns

Chip Select Low to End of Write

65

—

80

—

ns

Byte Enable Low to End of Write

65

—

80

—

ns

Address Set-up Time

0

—

0

—

ns

Address Hold from End of Write

0

—

0

—

ns

Write Pulse Width

55

—

70

—

ns

Data Valid to End of Write

30

—

40

—

ns

Data Hold Time

0

—

0

—

ns

(1)

Write Enable High to Output in Low-Z

5

—

5

—

ns

(1)

Write Enable Low to Output in High-Z

—

25

—

30

ns

NOTE:

3771 tbl 10

1. This parameter is guaranteed by device characterization, but is not production tested.

TIMING WAVEFORM OF READ CYCLE NO. 1

(1,2,3)

NOTES:

1.

WE is HIGH for Read Cycle.

2. Device is continuously selected,

CS is LOW.

3.

OE, BHE, and BLE are LOW.

ADDRESS

3771 drw 06