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IDT7164S30Y Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT7164S30Y Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 9 page 6.1 8 IDT7164S/L CMOS STATIC RAM 64K (8K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1 ( WE WE CONTROLLED TIMING) (1, 2, 6) TIMING WAVEFORM OF WRITE CYCLE NO. 2 ( CS CS CONTROLLED TIMING) (1, 2) NOTES: 1. WE, CS1 or CS2 must be inactive during all address transitions. 2. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2. 3. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals must not be applied. 5. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width is as short as the specified tWP. 7. Transition is measured ±200mV from steady state. ADDRESS tWC tWHZ(7) 2967 drw 08 CS1 DATA OUT CS2 tAS tAW tWR1(3) WE tWP tOW(7) DATA IN tDH1, 2 tDW DATA VALID (4) (6) 2967 drw 09 ADDRESS CS1 CS2 tWC tAS WE tCW tWR2 (3) tAW DATA IN tDH1,2 tDW DATA VALID tWR1 (3) (5) |
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