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IDT7187S55DB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT7187S55DB Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 8 page 6.2 6 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1 (1,2) TIMING WAVEFORM OF READ CYCLE NO. 2 (1,3) NOTES: 1. WE is HIGH for Read cycle. 2. CS is LOW for Read cycle. 3. Address valid prior to or coincident with CS transition LOW. 4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2. 5. All Read cycle timings are referenced from the last valid address to the first transitioning address. 2986 drw 07 ADDRESS DATA tRC tAA OUT tOH PREVIOUS DATA VALID DATA VALID (5) 2986 drw 08 DATAOUT CS tACS (4) tLZ (4) HZ t tPD t PU ICC ISB SUPPLY CURRENT VCC t RC (5) HIGH IMPEDANCE DATA VALID AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges) 7187S25 7187S35/45 (1) 7187S55 (1) 7187S70 (1) 7187S85 (1) 7187L25 7187L35/45 (1) 7187L55 (1) 7187L70 (1) 7187L85 (1) Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 25 — 35/45 — 55 — 70 — 85 — ns tCW Chip Select to End-of-Write 20 — 25/40 — 50 — 55 — 65 — ns tAW Address Valid to End-of-Write 20 — 25/40 — 50 — 55 — 65 — ns tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns tWP Write Pulse Width 20 — 20/25 — 35 — 40 — 45 — ns tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns tDW Data Valid to End-of-Write 15 — 15/25 — 25 — 30 — 35 — ns tDH Data Hold Time 5 — 5 — 5 — 5 — 5 — ns tWZ (2) Write Enable to Output in High-Z — 12 — 15/30 — 30 — 30 — 40 ns tOW (2) Output Active from End-of-Write 0 — 0 — 0 — 0 — 0 — ns NOTES: 2986 tbl 12 1. –55 °C to +125°C temperature range only. 2. This parameter guaranteed but not tested. |
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