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IDT7187L55DB Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7187L55DB Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 8 page 6.2 7 IDT7187S/L CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 ( WE WE CONTROLLED TIMING) (1,2,3,4) NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). TIMING WAVEFORM OF WRITE CYCLE NO. 2 ( CS CS CONTROLLED TIMING) (1,2,4) CS 2986 drw 09 tAW tWR t DW DATA IN ADDRESS tWC WE tWP t DH DATA OUT t WZ tOW tAS (5) VALID DATA (5) tWR CS 2986 drw 10 tAW t DW DATA IN ADDRESS t WC WE tCW t DH AS t t VALID DATA (3) |
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