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IDT71B74S15Y Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT71B74S15Y Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 9 page 14.1 5 IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is continuously active, OE is LOW. 5. Transition is measured ±200mV from steady state. TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4) 3013 drw 10 ADDRESS tRC tAA tOH DATAOUT tOH DATAOUT VALID TIMING WAVEFORM OF READ CYCLE NO. 1(1) 3013 drw 09 ADDRESS CS OE tRC tAA t OHZ (5) tOE DATAOUT tACS t CLZ (5) t CHZ (5) tOLZ (5) t OH DATAOUT VALID (3) AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%) 71B74S8 71B74S10 71B74S12 71B74S15 71B74S20 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 8 — 10 — 12 — 15 — 20 — ns tAA Address Access Time — 8 — 10 — 12 — 15 — 20 ns tACS Chip Select Access Time — 6 — 7 — 8 — 8 — 10 ns tCLZ (1) Chip Select to Output in Low-Z 2 — 2 — 2 — 3 — 3 — ns tOE Output Enable to Output Valid — 5 — 6 — 6 — 8 — 9 ns tOLZ (1) Output Enable to Output in Low-Z 2 — 2 — 2 — 2 — 2 — ns tCHZ (1) Chip Select to Output in High-Z — 4 — 5 — 5 — 7 — 8 ns tOHZ (1) Output Disable to Output in High-Z — 4 — 4 — 5 — 5 — 8 ns tOH Output Hold from Address Change 3 — 3 — 3 — 3 — 3 — ns NOTE: 3013 tbl 10 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. |
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