6.42

7

IDT71V016SA, 3.3V CMOS Static RAM

1 Meg (64K x 16-Bit)

Commercial and Industrial Temperature Ranges

NOTES:

1. A write occurs during the overlap of a LOW

CS, LOW BHE or BLE, and a LOW WE.

2.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the

CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

ADDRESS

CS

3834 drw 09

(2)

WE

BHE, BLE

ADDRESS

CS

3834 drw 10

(2)

WE

BHE, BLE